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FPGA Programming for Beginners

You're reading from   FPGA Programming for Beginners Bring your ideas to life by creating hardware designs and electronic circuits with SystemVerilog

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Product type Paperback
Published in Mar 2021
Publisher Packt
ISBN-13 9781789805413
Length 368 pages
Edition 1st Edition
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Author (1):
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Frank Bruno Frank Bruno
Author Profile Icon Frank Bruno
Frank Bruno
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Toc

Table of Contents (16) Chapters Close

Preface 1. Section 1: Introduction to FPGAs and Xilinx Architectures
2. Chapter 1: Introduction to FPGA Architectures and Xilinx Vivado FREE CHAPTER 3. Section 2: Introduction to Verilog RTL Design, Simulation, and Implementation
4. Chapter 2: Combinational Logic 5. Chapter 3: Counting Button Presses 6. Chapter 4: Let's Build a Calculator 7. Chapter 5: FPGA Resources and How to Use Them 8. Chapter 6: Math, Parallelism, and Pipelined Design 9. Section 3: Interfacing with External Components
10. Chapter 7: Introduction to AXI 11. Chapter 8: Lots of Data? MIG and DDR2 12. Chapter 9: A Better Way to Display – VGA 13. Chapter 10: Bringing It All Together 14. Chapter 11: Advanced Topics 15. Other Books You May Enjoy

Questions

  1. If we have a large dynamic range in our numbers, what are we better off using?

    a. Integers

    b. Fixed point

    c. Floating point

    d. Imaginary

  2. Which order represents the number complexity from least complex to most complex?

    a. Fixed point, integers, floating point

    b. Integer, fixed point, floating point

    c. Floating point, fixed point, integer

    d. Integer, floating point, fixed point

  3. The following code is an example of what kind of design?
    always @(posedge clk) begin
      if (stage[0]) out[0] <= fp_out[0];
      if (stage[1]) out[1] <= out[0] + fp_out[1];
      if (stage[2]) out[2] <= out[1] + out[0] + fp_out[2];
    end

    a. Pipelined

    b. Parallel

    c. State machine

  4. The following code is an example of what kind of design?
    always @(posedge clk) begin
      for (int i = 0; i < 128; i++) dout[i] <= din[i*2] + din[i*2+1];
    end 

    a. Pipelined

    b. Parallel

    c. State machine

  5. Which of the following signals makes up an AXI streaming interface?

    a. tdata

    b. tvalid...

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