Combinational Logic

Designs are typically composed of combinational and sequential logic. In Chapter 2, FPGA Programming Languages and Tools, we saw how combinational logic is made up of simple gates and created a simple design to show the gate functions on the board. In contrast, it is observed that sequential logic maintains a state, usually based on a clock edge, but it can be level-based as well, as we will discuss when we learn what not to do when inferring sequential logic.

In this chapter, we are going to explore how to write a complete SystemVerilog and VHDL module from scratch that can perform some basic real-world combinational logic operations that you may use one day in your actual designs.

We are going to cover the following main topics:

• Creating FPGA designs
• Understanding the basics of HDL design
• Project 2 – Creating combinational logic