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FPGA Programming for Beginners

You're reading from   FPGA Programming for Beginners Bring your ideas to life by creating hardware designs and electronic circuits with SystemVerilog

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Product type Paperback
Published in Mar 2021
Publisher Packt
ISBN-13 9781789805413
Length 368 pages
Edition 1st Edition
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Author (1):
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Frank Bruno Frank Bruno
Author Profile Icon Frank Bruno
Frank Bruno
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Toc

Table of Contents (16) Chapters Close

Preface 1. Section 1: Introduction to FPGAs and Xilinx Architectures
2. Chapter 1: Introduction to FPGA Architectures and Xilinx Vivado FREE CHAPTER 3. Section 2: Introduction to Verilog RTL Design, Simulation, and Implementation
4. Chapter 2: Combinational Logic 5. Chapter 3: Counting Button Presses 6. Chapter 4: Let's Build a Calculator 7. Chapter 5: FPGA Resources and How to Use Them 8. Chapter 6: Math, Parallelism, and Pipelined Design 9. Section 3: Interfacing with External Components
10. Chapter 7: Introduction to AXI 11. Chapter 8: Lots of Data? MIG and DDR2 12. Chapter 9: A Better Way to Display – VGA 13. Chapter 10: Bringing It All Together 14. Chapter 11: Advanced Topics 15. Other Books You May Enjoy

Questions

  1. A packed array is used to infer memories. True or false?
  2. A break statement can be used in a for loop when?

    a) Any time.

    b) If it's possible to rewrite the for loop in such a way as to not need the break.

    c) Only if you can reverse the direction of the loop; that is, go from low to high instead of high to low.

  3. Size the add_unsigned, add_signed, and mult signals:
    Logic unsigned [7:0] a_unsigned;
    logic unsigned [7:0] b_unsigned;
    logic signed [7:0] a_signed;
    logic signed [7:0] b_signed;
    assign add_unsigned = a_unsigned + b_unsigned;
    assign add_signed = a_signed + b_signed;
    assign mult = a_unsigned * b_unsigned;
  4. Division is a very costly operation. Look at the supported Vivado constructs in the Vivado Synthesis manual (Further reading). Can you easily replace the multiply operation with a division operation? What is possible without custom code?

Challenge

Look at the following add_sub module:

  logic signed [BITS/2-1:0]   ...
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