You're reading from Architecting and Building High-Speed SoCs Design, develop, and debug complex FPGA based systems-on-chip

Product type Paperback

Published in Dec 2022

Publisher Packt

ISBN-13 9781801810999

Length 426 pages

Edition 1st Edition

Tools

FPGA

Concepts

Design

Author (1):

Mounir Maaref

View More author details

Table of Contents (20) Chapters

Preface

1. Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs

2. Chapter 1: Introducing FPGA Devices and SoCs FREE CHAPTER

3. Chapter 2: FPGA Devices and SoC Design Tools

4. Chapter 3: Basic and Advanced On-Chip Busses and Interconnects

5. Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects

6. Chapter 5: Basic and Advanced SoC Interfaces

7. Part 2: Implementing High-Speed SoC Designs in an FPGA

8. Chapter 6: What Goes Where in a High-Speed SoC Design

9. Chapter 7: FPGA SoC Hardware Design and Verification Flow

10. Chapter 8: FPGA SoC Software Design Flow

11. Chapter 9: SoC Design Hardware and Software Integration

12. Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

13. Chapter 10: Building a Complex SoC Hardware Targeting an FPGA

14. Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC

15. Chapter 12: Building a Complex Software with an Embedded Operating System Flow

16. Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs

17. Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs

18. Index

Why subscribe?

19. Other Books You May Enjoy

Questions

Answer the following questions to test your knowledge of this chapter:

How is communication established between the main ETS SoC software and the hardware accelerator? Are there any alternative approaches you can think of?
How can we augment the capabilities of the proposed microarchitecture and scale it for future needs?
Why is the TS field used in the ETMP UDP packet?
Which field in the ETMP UDP packet is processed better in hardware instead of the MicroBlaze software? Why?
What are the advantages of starting the ETS SoC design from a template preset?
Describe the steps needed to augment the number of IPC interrupts between the Cortex-A9 and the MicroBlaze processors from 8 to 16 interrupts.
What is the frequency we chose to run the PL logic at? How can we increase it to 125 MHz?
How can we check that the aforementioned increase of the PL logic frequency to 125 MHz is okay for the ETS SoC project?
How are the PL interrupts targeting...

The rest of the chapter is locked

You're reading from Architecting and Building High-Speed SoCs Design, develop, and debug complex FPGA based systems-on-chip

Table of Contents (20) Chapters

Questions

Authors (1)

Personalised recommendations for you

You're reading from Architecting and Building High-Speed SoCs Design, develop, and debug complex FPGA based systems-on-chip

Table of Contents (20) Chapters

Questions

Unlock this book and the full library FREE for 7 days

Authors (1)

Personalised recommendations for you