Embedded OS software design flow for Xilinx FPGA-based SoCs

In Chapter 8, FPGA SoC Software Design Flow, we covered the design flow of a piece of bare-metal embedded software targeting the Electronic Trading System (ETS) SoC. In this chapter, we will go over the steps required to build a Real-Time Operating System (RTOS)-based software application targeting an FPGA SoC. We will perform the entire design flow within the Vitis environment and choose FreeRTOS as the embedded operating system (OS). The design flow can start from a hardware design previously performed in the Vivado environment that has been exported as an XSA archive file (such as the ETS SoC design example). This is then chosen in the Vitis IDE as hosting hardware for the SoC. An alternative method is to choose a Zynq-7000 SoC demo board as the target hardware and perform the necessary steps to create the required framework, as will be detailed in this chapter. Follow these steps to design a FreeRTOS-based SoC software...