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Architecting and Building High-Speed SoCs

You're reading from   Architecting and Building High-Speed SoCs Design, develop, and debug complex FPGA based systems-on-chip

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Product type Paperback
Published in Dec 2022
Publisher Packt
ISBN-13 9781801810999
Length 426 pages
Edition 1st Edition
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Author (1):
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Mounir Maaref Mounir Maaref
Author Profile Icon Mounir Maaref
Mounir Maaref
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Toc

Table of Contents (20) Chapters Close

Preface 1. Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
2. Chapter 1: Introducing FPGA Devices and SoCs FREE CHAPTER 3. Chapter 2: FPGA Devices and SoC Design Tools 4. Chapter 3: Basic and Advanced On-Chip Busses and Interconnects 5. Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects 6. Chapter 5: Basic and Advanced SoC Interfaces 7. Part 2: Implementing High-Speed SoC Designs in an FPGA
8. Chapter 6: What Goes Where in a High-Speed SoC Design 9. Chapter 7: FPGA SoC Hardware Design and Verification Flow 10. Chapter 8: FPGA SoC Software Design Flow 11. Chapter 9: SoC Design Hardware and Software Integration 12. Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs
13. Chapter 10: Building a Complex SoC Hardware Targeting an FPGA 14. Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC 15. Chapter 12: Building a Complex Software with an Embedded Operating System Flow 16. Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs 17. Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs 18. Index 19. Other Books You May Enjoy

Addressing the system coherency and using the Cortex-A9 ACP port

In this chapter, the focus for the hardware acceleration is to find ways to closely integrate the PL logic hardware accelerator with the Cortex-A9 cluster and build a more direct path between software and the acceleration hardware. This direct path should be without paying the penalty of using non-cacheable memory for data shared between the Cortex-A9 and its hardware accelerators. Using cacheable memory without any cache coherency support from the hardware imposes some performance penalties. Such sharing requires some form of synchronization between the Cortex-A9 and the PL Accelerators; for example, by using cache maintenance operation in the Cortex-A9 software. This is required following every update to the common data variables between the Cortex-A9 software and the PL hardware accelerator. The way this close integration can be achieved in the Zynq-7000 SoC is through the ACP, which provides a direct coherent path...

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