You're reading from Architecting and Building High-Speed SoCs Design, develop, and debug complex FPGA based systems-on-chip

Product type Paperback

Published in Dec 2022

Publisher Packt

ISBN-13 9781801810999

Length 426 pages

Edition 1st Edition

Tools

FPGA

Concepts

Design

Author (1):

Mounir Maaref

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Table of Contents (20) Chapters

Preface

1. Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs

2. Chapter 1: Introducing FPGA Devices and SoCs FREE CHAPTER

3. Chapter 2: FPGA Devices and SoC Design Tools

4. Chapter 3: Basic and Advanced On-Chip Busses and Interconnects

5. Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects

6. Chapter 5: Basic and Advanced SoC Interfaces

7. Part 2: Implementing High-Speed SoC Designs in an FPGA

8. Chapter 6: What Goes Where in a High-Speed SoC Design

9. Chapter 7: FPGA SoC Hardware Design and Verification Flow

10. Chapter 8: FPGA SoC Software Design Flow

11. Chapter 9: SoC Design Hardware and Software Integration

12. Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

13. Chapter 10: Building a Complex SoC Hardware Targeting an FPGA

14. Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC

15. Chapter 12: Building a Complex Software with an Embedded Operating System Flow

16. Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs

17. Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs

18. Index

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Summary

In this chapter, we looked at the key security features that are available in the Zynq-7000 SoC FPGA. We saw that these are threefold: FPGA-specific hardware features, the ARM TrustZone-based framework, and the Secure software execution environment. We covered the secure booting process and how the software and hardware images can be protected using encryption and authentication. Then, we examined how, at boot time, the FPGA features are used to establish the root of trust, decrypt the images, authenticate them, and then load the FSBL and optionally configure the FPGA with the secure bitstream file. We also delved into the Secure and NS software execution worlds and how they interact with each other via a Secure monitor. We examined the ARM TrustZone and the hardware protection mechanism used to make peripherals Secure or NS and how these transactions are qualified at runtime by the AXI and APB bus protocols. We presented a typical Secure system that combines the PS and PL...

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Table of Contents (20) Chapters

Summary

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Table of Contents (20) Chapters

Summary

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