Index
Symbols
$error or $fatal
using, in synthesis 490, 491
A
active low signal 120
adder
implementing 97
ADT7420 IP
developing 279, 280
Advanced eXtensible Interface (AXI) 236, 269
streaming interfaces 253, 254, 270
Advanced Silicon Modular Block (ASMBL) architecture 20
advanced SystemVerilog constructs
block labels, using 481, 482
code, skipping with continue 484
components, interfacing with interface construct 476-480
constants, using 484, 485
exploring 476
loop, exiting with disable statement 483, 484
looping, with do�while loops 482, 483
looping, with for loops 482
operators, packing 485, 486
structures, using 480, 481
advanced verification constructs
$error or $fatal, using in synthesis 490, 491
assertions 490
exploring 487
formatting enhancements, displaying 489, 490
SystemVerilog queues 487-489
analog-to-digital converter (ADC) 192
Application Specific...