Chapter 7. Generating Code for Target Architecture
The code generated by the compiler finally has to execute on the target machines. The abstract form of the LLVM IR helps to generate code for various architectures. The target machine can be anything – CPU, GPU, DSP's, and so on. The target machine has some defining aspects such as the register sets, the instruction set, the calling convention of the function, and the instruction pipeline. These aspects or properties are generated using the tablegen tool so that they can be used easily while programming code generation for the machine.
LLVM has a pipeline structure for the backend, where instructions travel through phases—from the LLVM IR to SelectionDAG, then to MachineDAG, then to MachineInstr, and finally to MCInst. The IR is converted to SelectionDAG. SelectionDAG then goes through legalization and optimizations. After this stage, the DAG nodes are mapped to target instructions (instruction selection)....
