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LLVM Essentials

You're reading from   LLVM Essentials Become familiar with the LLVM infrastructure and start using LLVM libraries to design a compiler

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Product type Paperback
Published in Dec 2015
Publisher
ISBN-13 9781785280801
Length 166 pages
Edition 1st Edition
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Authors (4):
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Suyog Sarda Suyog Sarda
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Suyog Sarda
Mayur Pandey Mayur Pandey
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Mayur Pandey
David Farago David Farago
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David Farago
John Criswell John Criswell
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John Criswell
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Toc

Scheduling and emitting machine instructions


Until now, we have been performing the operations on DAG. Now, for the machine to execute, we need to convert the DAGs into instruction that the machine can execute. One step towards it is emitting the list of instructions into MachineBasicBlock. This is done by the Scheduler, whose goal is to linearize the DAGs. The scheduling is dependent on the target architecture, as certain Targets will have target specific hooks which can affect the scheduling.

The class InstrEmitter::EmitMachineNode takes SDNode *Node as one of the input parameters for which it will be emitting machine instructions of the class MachineInstr. These instructions are emitted into a MachineBasicBlock.

The function calls EmitSubregNode, EmitCopyToRegClassNode and EmitRegSequence for the handling of subreg insert/extract, COPY_TO_REGCLASS, and REG_SEQUENCE respectively.

The call MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II); is used to build the Machine Instruction...

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