When a peripheral asserts an interrupt, the interrupt controller is triggered to latch this event. The electrical characteristics that it uses to trigger the hardware interrupt in the CPU fall into two broad categories:
- Level-triggered: The interrupt is triggered when the level changes (from inactive to active or asserted); until it's deasserted, the line remains in the asserted state. This happens even after your handler returns; if the line is still asserted, you will get the interrupt again.
- Edge-triggered: The interrupt triggers only once when the level changes from inactive to active.
Additionally, the interrupt could be high or low triggered, on the rising or falling (clock) edge. The kernel allows this to be configured and specified via additional flags such as IRQF_TRIGGER_NONE, IRQF_TRIGGER_RISING, IRQF_TRIGGER_FALLING, IRQF_TRIGGER_HIGH, IRQF_TRIGGER_LOW, and so on. These low...
