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Practical Hardware Pentesting

You're reading from   Practical Hardware Pentesting A guide to attacking embedded systems and protecting them against the most common hardware attacks

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Product type Paperback
Published in Apr 2021
Publisher Packt
ISBN-13 9781789619133
Length 382 pages
Edition 1st Edition
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Author (1):
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Jean-Georges Valle Jean-Georges Valle
Author Profile Icon Jean-Georges Valle
Jean-Georges Valle
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Toc

Table of Contents (20) Chapters Close

Preface 1. Section 1: Getting to Know the Hardware
2. Chapter 1: Setting Up Your Pentesting Lab and Ensuring Lab Safety FREE CHAPTER 3. Chapter 2: Understanding Your Target 4. Chapter 3: Identifying the Components of Your Target 5. Chapter 4: Approaching and Planning the Test 6. Section 2: Attacking the Hardware
7. Chapter 5: Our Main Attack Platform 8. Chapter 6: Sniffing and Attacking the Most Common Protocols 9. Chapter 7: Extracting and Manipulating Onboard Storage 10. Chapter 8: Attacking Wi-Fi, Bluetooth, and BLE 11. Chapter 9: Software-Defined Radio Attacks 12. Section 3: Attacking the Software
13. Chapter 10: Accessing the Debug Interfaces 14. Chapter 11: Static Reverse Engineering and Analysis 15. Chapter 12: Dynamic Reverse Engineering 16. Chapter 13: Scoring and Reporting Your Vulnerabilities 17. Chapter 14: Wrapping It Up – Mitigations and Good Practices 18. Assessments 19. Other Books You May Enjoy

Understanding I2C

I2C (pronounced as I-two-see, or I-square-see), short for Inter-Integrated Circuit, is a protocol that was invented by Phillips in the early 80s to be used in televisions. Due to its easy topology and low part count, it is now widely adopted.

Mode of operation

I2C connects chips with two wires: one is data (bidirectional) and the other is clock (of course, with a shared ground). On the bus, one chip acts as the master and the others as slaves (but they can exchange this role if this functionality is foreseen).

Physical layer

A very important feature on the I2C bus is that both lines (classically called Serial Data (SDA) for the data line and Serial Clock (SCL) for the clock line) are pulled up. This means they both have a resistor to the logical positive rail (also called VCC or VDD) in order to guarantee that the bus is high when no chip is pulling it to ground level (low). The bus normally uses a bus topology, but at low speeds, it is possible to use...

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