Creating SystemVerilog modules
At the heart of every design are the modules that compose it. From the testbench that's used to verify the design to any instantiated components, they are all declared somewhere as a module. For the example design we'll be covering in this chapter, we'll be creating a set of modules representing the functions that we can access via the buttons and switches on the evaluation board. We'll use these switches to set values, and we'll use five buttons to perform operations.
Let's take a look at the components of a module declaration:
module project_2
#(parameter SELECTOR,
Parameter BITS = 16)
(input wire [BITS-1:0] SW,
input wire BTNC,
input wire ...
