Summary

In this chapter, we’ve learned the basics of ASICs and FPGAs, how they are built, and when they make monetary sense. We’ve looked at the basic building blocks and gates, and learned how larger components are built from these fundamental cells. We’ve also identified other FPGA components, namely, DSP, BRAM, and PLLs, which we will use throughout the book.

The next chapter will discuss SystemVerilog/Verilog and VHDL, detailing some of the commonalities and differences and why you might pick one over the other. We’ll load up Vivado, develop our first application, and run it.