Summary

In this chapter, we had a brief discussion about how a target architecture machine can be represented in LLVM. We saw the ease of using tablegen in organizing data such as register sets, instruction sets, calling conventions, and so on, for a given target. The llvm-tablegen then converts these target descriptor .td fies into enums, which can be used in program logic such as frame lowering, instruction selection, instruction printing, and so on. More detailed and complex architectures like ARM and X86 can give insight on a detailed description of the target.

In the first chapter, we tried a basic exercise to get hands-on with various tools provided by the LLVM infrastructure. In the subsequent chapters, that is, Chapter 2, Building LLVM IR, and Chapter 3, Advanced LLVM IR, we used APIs provided by LLVM to emit IRs. Readers can use those APIs in their frontend to convert their language to LLVM IR. In Chapter 5, Advanced IR Block Transformations, we got used to Pass Pipeline for IR optimization...