Comparing bytecode with intermediate code

In Chapter 9, Intermediate Code Generation, we generated machine-independent intermediate code using abstract three-address instructions. Bytecode instruction sets are in between the three-address intermediate code and a real hardware instruction set in their complexity. A single three-address instruction may map to multiple bytecode instructions. This refers to both the direct translation of any instance of a three-address instruction, as well as to the fact that there may be several bytecode instruction opcodes that handle various special cases of a given three-address opcode. Bytecode is generally more involved than intermediate code, even if it manages to avoid the complexities of operand addressing modes found on a lot of CPUs.

Many or most bytecode instruction sets explicitly or implicitly use (virtual, logical) registers, although bytecode machines are usually far simpler than CPU hardware in terms of the number of registers and...