Search icon CANCEL
Subscription
0
Cart icon
Your Cart (0 item)
Close icon
You have no products in your basket yet
Arrow left icon
Explore Products
Best Sellers
New Releases
Books
Videos
Audiobooks
Learning Hub
Conferences
Free Learning
Arrow right icon
Arrow up icon
GO TO TOP
Architecting and Building High-Speed SoCs

You're reading from   Architecting and Building High-Speed SoCs Design, develop, and debug complex FPGA based systems-on-chip

Arrow left icon
Product type Paperback
Published in Dec 2022
Publisher Packt
ISBN-13 9781801810999
Length 426 pages
Edition 1st Edition
Tools
Concepts
Arrow right icon
Author (1):
Arrow left icon
Mounir Maaref Mounir Maaref
Author Profile Icon Mounir Maaref
Mounir Maaref
Arrow right icon
View More author details
Toc

Table of Contents (20) Chapters Close

Preface 1. Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
2. Chapter 1: Introducing FPGA Devices and SoCs FREE CHAPTER 3. Chapter 2: FPGA Devices and SoC Design Tools 4. Chapter 3: Basic and Advanced On-Chip Busses and Interconnects 5. Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects 6. Chapter 5: Basic and Advanced SoC Interfaces 7. Part 2: Implementing High-Speed SoC Designs in an FPGA
8. Chapter 6: What Goes Where in a High-Speed SoC Design 9. Chapter 7: FPGA SoC Hardware Design and Verification Flow 10. Chapter 8: FPGA SoC Software Design Flow 11. Chapter 9: SoC Design Hardware and Software Integration 12. Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs
13. Chapter 10: Building a Complex SoC Hardware Targeting an FPGA 14. Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC 15. Chapter 12: Building a Complex Software with an Embedded Operating System Flow 16. Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs 17. Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs 18. Index 19. Other Books You May Enjoy

Early SoC architecture modeling and the golden model

When targeting an FPGA for an SoC implementation, reimplementing the design takes a matter of days or even sometimes just hours. It involves changing the behavior of an RTL block or drop in a verified IP. Doing so when the target technology is an ASIC is a lengthy process with significant costs in terms of resources and budget.

We will introduce system modeling in the closing section of this chapter as it is part of the architecture development in general and it is also becoming a time-to-market solution for system implementations that take a long time to accomplish, specifically when targeting an ASIC technology. The industry is exploiting the availability of detailed system models of processors, interconnects, and all the IP elements of an SoC to build virtual SoCs. These are system models that emulate the functional behavior of an SoC in software simulation. Many frameworks are available that can put system models together...

lock icon The rest of the chapter is locked
Register for a free Packt account to unlock a world of extra content!
A free Packt account unlocks extra newsletters, articles, discounted offers, and much more. Start advancing your knowledge today.
Unlock this book and the full library FREE for 7 days
Get unlimited access to 7000+ expert-authored eBooks and videos courses covering every tech area you can think of
Renews at $19.99/month. Cancel anytime
Banner background image