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Embedded Systems Architecture

You're reading from   Embedded Systems Architecture Design and write software for embedded devices to build safe and connected systems

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Product type Paperback
Published in Jan 2023
Publisher Packt
ISBN-13 9781803239545
Length 342 pages
Edition 2nd Edition
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Author (1):
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Daniele Lacamera Daniele Lacamera
Author Profile Icon Daniele Lacamera
Daniele Lacamera
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Table of Contents (18) Chapters Close

Preface 1. Part 1 – Introduction to Embedded Systems Development
2. Chapter 1: Embedded Systems – A Pragmatic Approach FREE CHAPTER 3. Chapter 2: Work Environment and Workflow Optimization 4. Part 2 – Core System Architecture
5. Chapter 3: Architectural Patterns 6. Chapter 4: The Boot-Up Procedure 7. Chapter 5: Memory Management 8. Part 3 – Device Drivers and Communication Interfaces
9. Chapter 6: General-Purpose Peripherals 10. Chapter 7: Local Bus Interfaces 11. Chapter 8: Power Management and Energy Saving 12. Chapter 9: Distributed Systems and IoT Architecture 13. Part 4 – Multithreading
14. Chapter 10: Parallel Tasks and Scheduling 15. Chapter 11: Trusted Execution Environment 16. Index 17. Other Books You May Enjoy

The interrupt vector table

The interrupt vector table, often abbreviated to IVT or simply IV, is an array of pointers to functions associated by the CPU to handle specific exceptions, such as faults, system service requests from the application, and interrupt requests from peripherals. The IVT is usually located at the beginning of the binary image and thus is stored starting from the lowest address in the flash memory.

An interrupt request from a hardware component or peripheral will force the CPU to abruptly suspend the execution and execute the function at the associated position in the vector. For this reason, these functions are called interrupt service routines (or simply ISRs). Runtime exceptions and faults can be handled in the same way as hardware interrupts, so special service routines are associated with internal CPU triggers through the same table.

The order of the ISRs enumerated in the vector, and their exact positions depend on the CPU architecture, the microcontroller...

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