Understanding SPI

SPI, or serial-to-parallel interface, is a (usually minimum) three-wire bus. One acts as the clock (CLK), one as Master Out Slave In (MOSI), and one as Master In Slave Out (MISO). If multiple slaves are present in the bus, there is also an additional wire per slave called CS or SS (Chip Select or Slave Select, usually active low).

Here is how multiple slaves are connected:

Figure 6.12 – SPI general architecture

SPI only manages how the bits are transferred on the line; there is no logical layer in the protocol (like I2C has).

On systems where the speed of transfer is important, SPI can come in the QSPI flavor (queued SPI/quad SPI) where there are four data lines. You should note that some chips support both modes and can switch between them with internal commands (that is, commands in the data that are transported by SPI, not commands determined by the SPI protocol itself).

Now that we have seen how the chips are connected...