Search icon CANCEL
Subscription
0
Cart icon
Your Cart (0 item)
Close icon
You have no products in your basket yet
Save more on your purchases now! discount-offer-chevron-icon
Savings automatically calculated. No voucher code required.
Arrow left icon
Explore Products
Best Sellers
New Releases
Books
Videos
Audiobooks
Learning Hub
Conferences
Free Learning
Arrow right icon
Arrow up icon
GO TO TOP
FPGA Programming for Beginners

You're reading from   FPGA Programming for Beginners Bring your ideas to life by creating hardware designs and electronic circuits with SystemVerilog

Arrow left icon
Product type Paperback
Published in Mar 2021
Publisher Packt
ISBN-13 9781789805413
Length 368 pages
Edition 1st Edition
Languages
Tools
Arrow right icon
Author (1):
Arrow left icon
Frank Bruno Frank Bruno
Author Profile Icon Frank Bruno
Frank Bruno
Arrow right icon
View More author details
Toc

Table of Contents (16) Chapters Close

Preface 1. Section 1: Introduction to FPGAs and Xilinx Architectures
2. Chapter 1: Introduction to FPGA Architectures and Xilinx Vivado FREE CHAPTER 3. Section 2: Introduction to Verilog RTL Design, Simulation, and Implementation
4. Chapter 2: Combinational Logic 5. Chapter 3: Counting Button Presses 6. Chapter 4: Let's Build a Calculator 7. Chapter 5: FPGA Resources and How to Use Them 8. Chapter 6: Math, Parallelism, and Pipelined Design 9. Section 3: Interfacing with External Components
10. Chapter 7: Introduction to AXI 11. Chapter 8: Lots of Data? MIG and DDR2 12. Chapter 9: A Better Way to Display – VGA 13. Chapter 10: Bringing It All Together 14. Chapter 11: Advanced Topics 15. Other Books You May Enjoy

Deep dive on synchronization

In project 2, we dipped our toes into synchronizing a signal from an external source. In later designs, we'll be interfacing between multiple clock domains. For instance, in Chapter 5, FPGA Resources and How to Use Them, we'll be interfacing between our main logic and a DDR controller running on a different clock domain.

Why use multiple clocks?

There are several clocking considerations when architecting your FPGA design. Sometimes you are forced to use a given clock for an interface. For example, if you are designing something that interfaces to 10G Ethernet, somewhere in your design will be a multiple of 156.25 MHz or 322.27 MHz depending on if you are interfacing with the PCS or PMA layer. This is because data must be driven out at this frequency and arrives at this frequency.

Other times, you may be looking for high performance or lower power. Increasing your clock speed can increase your throughput or calculations per second if...

lock icon The rest of the chapter is locked
Register for a free Packt account to unlock a world of extra content!
A free Packt account unlocks extra newsletters, articles, discounted offers, and much more. Start advancing your knowledge today.
Unlock this book and the full library FREE for 7 days
Get unlimited access to 7000+ expert-authored eBooks and videos courses covering every tech area you can think of
Renews at $19.99/month. Cancel anytime