Chapter 2: Combinational Logic
Designs are typically composed of combinational and sequential logic. Combinational logic is made up simply of gates, as we saw in Chapter 1, Introduction to FPGA Architectures and Xilinx Vivado. Sequential logic maintains state, usually based on a clock edge, but it can be level-based as well, as we will discuss when we learn what not to do when inferring sequential logic.
In this chapter, we are going to explore writing a complete SystemVerilog module from scratch that can perform some basic real-world operations that you may use one day in your actual designs.
In this chapter, we are going to cover the following main topics:
- Creating SystemVerilog modules
- Introducing data types
- Packaging up code using functions
- Project – creating combinational logic
