MIT researchers built a 16-bit RISC-V compliant microprocessor from carbon nanotubes

Limitations in carbon nanotubes and how the researchers addressed them

According to the research paper, silicon exhibits additional properties as it can be easily doped but in the case of carbon nanotubes, they are small so it becomes difficult to dope them. Also, it is difficult to grow the nanotubes where they're needed and equally difficult to manipulate them or to place them in the right location. When carbon nanotubes are fabricated at scale, the transistors usually come with many defects that can affect the performance, so it becomes impractical to choose them. 

To overcome these,  MIT researchers invented new techniques to limit the defects and provide full functional control in fabricating CNFETs with the help of the processes in traditional silicon chip foundries. 

1. Firstly, the researchers made a silicon surface with metallic features that were large enough to let several nanotubes bridge the gaps between the metal. 
2. Then they placed a layer of material on top of the nanotubes and used with sonication to get  rid of the aggregates. Though the material took the aggregates with it, it left the underlying layer of nanotubes without getting them disturbed.
3. To limit nanotubes to where they were needed, the researchers etched off most of the layer of nanotubes and placed them where they were needed. They further added a variable layer of oxide on top of the nanotubes. 
4. The researchers also demonstrated a 16-bit microprocessor with more than 14,000 CNFETs that performs the same tasks similar to commercial microprocessors. 

Introduced DREAM technique to attain 99% of purity in carbon nanotubes

Advanced circuits need to have carbon nanotubes with around 99.999999 percent purity for becoming robust to failures, which is nearly impossible. The researchers introduced a technique called DREAM (“designing resiliency against metallic CNTs”) that positions metallic CNFETs in a way that they don’t disrupt computing. 

This way they relaxed the stringent purity requirement by around four orders of magnitude or 10,000 times, then they required carbon nanotubes at about 99.99 percent purity which was possible to attain.

Developed RINSE for cleansing the contamination on the chip

For CNFET fabrication, the carbon nanotubes are deposited in a solution onto a wafer along with predesigned transistor architectures. But in this process, carbon nanotubes stick randomly together to form big bundles that lead to the formation of contamination on the chip.  

To cleanse contamination, the researchers developed RINSE ( “removal of incubated nanotubes through selective exfoliation”). In this process, the wafer is pretreated with an agent that promotes carbon nanotube adhesion. Later, the wafer is coated with a polymer and is then dipped in a special solvent. It washes away the polymer that carries away the big bundles and single carbon nanotubes remain stuck to the wafer. The RINSE technique can lead to about a 250-times reduction in particle density on the chip as compared to other similar methods.

New chip design, RV16X-NANO handles 32 bit long instructions on RISC-V architecture

The researchers built a new chip design and drew insights based on the chip. According to the insights, few logical functions were less sensitive to metallic nanotubes than the others. The researchers modified an open-source RISC design tool to take this information into account. It resulted in a chip design that had none of the gates being most sensitive to metallic carbon nanotubes. 

Hence, the team named the chip as RV16X-NANO designed to handle the 32-bit-long instructions of the RISC-V architecture. They used more than 14,000 individual transistors for the RV16X-NANO, and every single one of those 14,000 gates did work as per the plan. The chip successfully executed a variant of the traditional "Hello World" program which is used as an introduction to the syntax of different programming languages.

In this paper, researchers have focused on ways to improve  their existing design. But the design needs to tolerate metallic nanotubes as it will have multiple nanotubes in each transistor. The design needs to be such that few nanotubes in bad orientations wouldn’t leave enough space for others to form functional contacts. 

Researchers major goal was to make single-nanotube transistors, which would require the ability to  control the location of their chip placement. This research proves that it is possible to integrate carbon nanotubes in the existing chipmaking processes, with additional electronics necessary for a processor to function. The researchers have started implementing their manufacturing techniques into a silicon chip foundry via a program by the DARPA (Defense Advanced Research Projects Agency).

To know more about this research, check out the official paper published. 

What’s new in IoT this week?

Intel’s 10th gen 10nm ‘Ice Lake’ processor offers AI apps, new graphics and best connectivity

Hot Chips 31: IBM Power10, AMD’s AI ambitions, Intel NNP-T, Cerebras largest chip with 1.2 trillion transistors and more

Alibaba’s chipmaker launches open source RISC-V based ‘XuanTie 910 processor’ for 5G, AI, IoT and self-driving applications