Other gotchas and how to avoid them

As we near the end of our journey, there are a few more things that we should look at, along with how we can detect them or avoid them altogether: inferring single-bit wires, bit-width mismatches, upgrading or downgrading Vivado messages, and handling timing closure.

Inferring single-bit wires

Since the advent of Verilog, it has always been legal to use a wire without defining it. This can happen if it is a port on an instantiate module. There is an example project: https://github.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/blob/main/CH14/SystemVerilog/build/inferred_wire.xpr.

You can see that I’ve created a variable-width adder module and connected three of them up:

adder #(4) u_add0 (.in0(SW[3:0]),  .in1(SW[7:4]), 
                   .out(add0_out));
adder #(4) u_add1 (.in0(SW[11:8]), .in1(SW[15:12]),
                   .out(add1_out));
adder #(5) u_add2 (.in0(add0_out), .in1(add1_out),
            ...