Summary
In this chapter, we looked at some more advanced and lesser-used SystemVerilog constructs. The main one is interfaces, which allow better design reuse and encapsulation. We investigated some more advanced looping, structures, and labels.
We also looked at some more advanced verification constructs. These will help you as your designs grow and get more complex.
Finally, we looked at some gotchas, how to avoid them, and some basics of timing closure.
You’ve now completed the book and should be able to tackle some tasks on your own. As I mentioned at the beginning, there are many community efforts, such as the Mister Project, that could use some people with FPGA knowledge. There are also projects you can try to tackle on your own to land a job. Whatever you choose, I hope that you find it as fun and rewarding as I do.
