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LLVM Essentials

You're reading from   LLVM Essentials Become familiar with the LLVM infrastructure and start using LLVM libraries to design a compiler

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Product type Paperback
Published in Dec 2015
Publisher
ISBN-13 9781785280801
Length 166 pages
Edition 1st Edition
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Authors (4):
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Suyog Sarda Suyog Sarda
Author Profile Icon Suyog Sarda
Suyog Sarda
Mayur Pandey Mayur Pandey
Author Profile Icon Mayur Pandey
Mayur Pandey
David Farago David Farago
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David Farago
John Criswell John Criswell
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John Criswell
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What this book covers

Chapter 1, Playing with LLVM, introduces you to the modular design of LLVM and LLVM Intermediate Representation. In this chapter, we also look into some of the tools that LLVM provides.

Chapter 2, Building LLVM IR, introduces you to some basic function calls provided by the LLVM infrastructure to build LLVM IR. This chapter demonstrates building of modules, functions, basic blocks, condition statements, and loops using LLVM APIs.

Chapter 3, Advanced LLVM IR, introduces you to some advanced IR paradigms. This chapter explains advanced IR to the readers and shows how LLVM function calls can be used to emit them in the IR.

Chapter 4, Basic IR Transformations, deals with basic transformation optimizations at the IR level using the LLVM optimizer tool opt and the LLVM Pass infrastructure. You will learn how to use the information of one pass in another and then look into Instruction Simplification and Instruction Combining Passes.

Chapter 5, Advanced IR Block Transformations, deals with optimizations at block level on IR. We will discuss various optimizations such as Loop Optimizations, Scalar Evolution, Vectorization, and so on, followed by the summary of this chapter.

Chapter 6, IR to Selection DAG phase, takes you on a journey through the abstract infrastructure of a target-independent code generator. We explore how LLVM IR is converted to Selection DAG and various phases thereafter. It also introduces you to instruction selection, scheduling, register allocation, and so on.

Chapter 7, Generating Code for Target Architecture, introduces the readers to the tablegen concept. It shows how target architecture specifications such as register sets, instruction sets, calling conventions, and so on can be represented using tablegen, and how the output of tablegen can be used to emit code for a given architecture. This chapter can be used by readers as a reference for bootstrapping a target machine code generator.

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