Questions

1. A packed array in SystemVerilog is used to infer memories. True or false?
2. When can a break or exit statement be used in a for loop?
   1. Any time.
   2. If it’s possible to rewrite the for loop in such a way as to not need the break.
   3. Only if you can reverse the direction of the loop; that is, go from low to high instead of high to low.
3. Size the add_unsigned, add_signed, and mult signals:

   logic unsigned [7:0] a_unsigned;
   logic unsigned [7:0] b_unsigned;
   logic signed [7:0] a_signed;
   logic signed [7:0] b_signed;
   assign add_unsigned = a_unsigned + b_unsigned;
   assign add_signed = a_signed + b_signed;
   assign mult = a_unsigned * b_unsigned;
   

4. Division is a very costly operation. Look at the supported Vivado constructs in the Vivado Synthesis manual (Further reading). Can you easily replace the multiply operation with a division operation? What is possible without custom code?