Creating FPGA designs

At the heart of every design are the modules and entities that compose it. From the testbench that’s used to verify the design to any instantiated components, they are all declared somewhere as a module or entity. For the example design that we’ll be covering in this chapter, we’ll be creating a set of underlying modules representing the functions that we can access via the buttons and switches on the evaluation board. We’ll use these switches to set values, and we’ll use five buttons to perform operations.

Project 1, Logic_ex, in Chapter 2 was our first project, so we’ll be starting our official project numbering here with project_2. Let’s look at the parts of a SystemVerilog module declaration:

module project_2
#(parameter SELECTOR,
  Parameter BITS = 16)
(input wire [BITS-1:0]          SW,
 input wire                     BTNC,
 input wire                     BTNU,
 input wire                     BTNL...