Sample backend

To understand target code generation, we define a simple RISC-type architecture TOY machine with minimal registers, say r0-r3, a stack pointer SP, a link register, LR (for storing the return address); and a CPSR – current state program register. The calling convention of this toy backend is similar to the ARM thumb-like architecture—arguments passed to the function will be stored in register sets r0-r1, and the return value will be stored in r0.

Defining registers and register sets

Register sets are defined using the tablegen tool. Tablegen helps to maintain large number of records of domain specific information. It factors out the common features of these records. This helps in reducing duplication in the description and forms a structural way of representing domain information. Please visit http://llvm.org/docs/TableGen/ to understand tablegen in detail. TableGen files are interpreted by the TableGen binary: llvm-tblgen.

We have described our sample backend in the preceding...