You're reading from Architecting and Building High-Speed SoCs Design, develop, and debug complex FPGA based systems-on-chip

Product type Paperback

Published in Dec 2022

Publisher Packt

ISBN-13 9781801810999

Length 426 pages

Edition 1st Edition

Tools

FPGA

Concepts

Design

Author (1):

Mounir Maaref

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Table of Contents (20) Chapters

Preface

1. Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs

2. Chapter 1: Introducing FPGA Devices and SoCs FREE CHAPTER

3. Chapter 2: FPGA Devices and SoC Design Tools

4. Chapter 3: Basic and Advanced On-Chip Busses and Interconnects

5. Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects

6. Chapter 5: Basic and Advanced SoC Interfaces

7. Part 2: Implementing High-Speed SoC Designs in an FPGA

8. Chapter 6: What Goes Where in a High-Speed SoC Design

9. Chapter 7: FPGA SoC Hardware Design and Verification Flow

10. Chapter 8: FPGA SoC Software Design Flow

11. Chapter 9: SoC Design Hardware and Software Integration

12. Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

13. Chapter 10: Building a Complex SoC Hardware Targeting an FPGA

14. Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC

15. Chapter 12: Building a Complex Software with an Embedded Operating System Flow

16. Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs

17. Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs

18. Index

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Software security aspects and how they integrate the hardware’s available features

From the processor perspective, the 32-bit physical address space (4 GB) is the same, but it has a 33rd bit that permits qualifying the address space accessed as Secure or NS. Also, the processor hardware is implemented as a dual virtual core, one of which is Secure; the other is NS. The hardware also implements a context-switching mechanism between the two virtual cores. This mechanism is known as Monitor mode. The NS bit set on the processor bus interface is a direct reflection of the actual virtual core performing the transaction. The NS virtual processor can only access NS peripherals, whereas the Secure one can view the full system resources. The following diagram shows the logical transition path between the Normal software execution mode and the Secure software execution mode, otherwise known as Normal world and Secure world, respectively:

Figure 11.5 –...

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You're reading from Architecting and Building High-Speed SoCs Design, develop, and debug complex FPGA based systems-on-chip

Table of Contents (20) Chapters

Software security aspects and how they integrate the hardware’s available features

Authors (1)

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Table of Contents (20) Chapters

Software security aspects and how they integrate the hardware’s available features

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Authors (1)

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