The complete TC3 code
We have discussed the design of TC3. Here, we present the code of a complete simulator. There are some slight differences between the descriptive fragments of code we described in the previous section and this more complete simulator. This is followed by a sample run of the simulator. The first part of the code defines the instruction modes and provides a simple source program that will be executed:
### TC3 CISC machine
### Demonstration register-to-memory architecture Designed 22 January 2022.
### Instruction formats and addressing modes
### Mode 0: NOP, STOP No operand length 1
### Mode 1: INC R1 Single register operand
### Mode 2: BEQ XXX Literal operand
### Mode 3: Reserved
### Mode 4: MOV r1,literal Two-operand, register...
