You're reading from Architecting and Building High-Speed SoCs Design, develop, and debug complex FPGA based systems-on-chip

Product type Paperback

Published in Dec 2022

Publisher Packt

ISBN-13 9781801810999

Length 426 pages

Edition 1st Edition

Tools

FPGA

Concepts

Design

Author (1):

Mounir Maaref

View More author details

Table of Contents (20) Chapters

Preface

1. Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs

2. Chapter 1: Introducing FPGA Devices and SoCs FREE CHAPTER

3. Chapter 2: FPGA Devices and SoC Design Tools

4. Chapter 3: Basic and Advanced On-Chip Busses and Interconnects

5. Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects

6. Chapter 5: Basic and Advanced SoC Interfaces

7. Part 2: Implementing High-Speed SoC Designs in an FPGA

8. Chapter 6: What Goes Where in a High-Speed SoC Design

9. Chapter 7: FPGA SoC Hardware Design and Verification Flow

10. Chapter 8: FPGA SoC Software Design Flow

11. Chapter 9: SoC Design Hardware and Software Integration

12. Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

13. Chapter 10: Building a Complex SoC Hardware Targeting an FPGA

14. Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC

15. Chapter 12: Building a Complex Software with an Embedded Operating System Flow

16. Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs

17. Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs

18. Index

Why subscribe?

19. Other Books You May Enjoy

Questions

Answer the following questions to test your knowledge of this chapter:

What are the main steps that need to be performed to start building the software for the ETS SoC project?
What are the main options available for XSA file generation? Explain the differences between them.
What needs to be done to generate the boot software for the ETS SoC project when the Vitis project is first created?
What is a domain in the Vitis IDE, what are the steps to create one, and what is it needed for?
What is a BSP and how is it set up in the Vitis IDE?
How can we add a library to a software project in Vitis and what are the build option requirements for it to be recognized?
Propose a data structure format for the ARE that meets the requirements of the microarchitecture of the ETS SoC design.
Is the IPC interrupt from the Cortex-A9 necessary for this system architecture to work?
Suggested another alternative IPC mechanism that avoids the IPC interrupts...

The rest of the chapter is locked

You're reading from Architecting and Building High-Speed SoCs Design, develop, and debug complex FPGA based systems-on-chip

Table of Contents (20) Chapters

Questions

Authors (1)

Personalised recommendations for you

You're reading from Architecting and Building High-Speed SoCs Design, develop, and debug complex FPGA based systems-on-chip

Table of Contents (20) Chapters

Questions

Unlock this book and the full library FREE for 7 days

Authors (1)

Personalised recommendations for you