Defining the distributed software microarchitecture for the ETS SoC processors
Thus far in this chapter, we have learned how a software project is created using the Vitis IDE, associated with a specific processor in the ETS SoC project, and how its BSP is configured. We can now delve into the software application-building process. We will develop a software microarchitecture for each processor core used in the ETS SoC design first. This will be based on the system architecture we developed in Chapter 6, What Goes Where in a High-Speed SoC Design, and the hardware implementation choices we made in Chapter 7, FPGA SoC Hardware Design and Verification Flow, such as the IPC mechanisms in both directions between the Cortex-A9 and the MicroBlaze PP processors. We can now revisit some remaining open items in the SoC system architecture. We have also defined the Electronic Trading Market Protocol (ETMP); therefore, the filtering tasks are easily identifiable by reading the UDP packet payload...