Index
As this ebook edition doesn't have fixed pagination, the page numbers below are hyperlinked for reference only, based on the printed edition of this book.
A
Acceleration Request Entry (ARE) 188, 265
Acceleration Request Queue (ARQ) 188
Acceleration Requests (ARE) 317
Accelerator Coherency Port (ACP) 312
accelerators port
used, for extending cache coherency at SoC level 88, 89
Accellera SystemC
used, for system modeling 171, 172
ACE-4
used, for extending cache coherency at SoC level 89
ACE bus protocol
cache line states, rules 73
characteristics 71-73
evolution 71
interface signals 74, 75
overview 71
supported transactions 76, 77
system implementation, example 77
Advanced Encryption Standards (AES) 328
Advanced Host Controller Interface (AHCI) 23
Advanced Peripheral Bus (APB) 52
Advanced System Bus (ASB) 52
Advance High-performance Bus (AHB) 52
Advance Microcontroller Bus Architecture...