You're reading from Architecting and Building High-Speed SoCs Design, develop, and debug complex FPGA based systems-on-chip

Product type Paperback

Published in Dec 2022

Publisher Packt

ISBN-13 9781801810999

Length 426 pages

Edition 1st Edition

Tools

FPGA

Concepts

Design

Author (1):

Mounir Maaref

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Table of Contents (20) Chapters

Preface

1. Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs

2. Chapter 1: Introducing FPGA Devices and SoCs FREE CHAPTER

3. Chapter 2: FPGA Devices and SoC Design Tools

4. Chapter 3: Basic and Advanced On-Chip Busses and Interconnects

5. Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects

6. Chapter 5: Basic and Advanced SoC Interfaces

7. Part 2: Implementing High-Speed SoC Designs in an FPGA

8. Chapter 6: What Goes Where in a High-Speed SoC Design

9. Chapter 7: FPGA SoC Hardware Design and Verification Flow

10. Chapter 8: FPGA SoC Software Design Flow

11. Chapter 9: SoC Design Hardware and Software Integration

12. Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

13. Chapter 10: Building a Complex SoC Hardware Targeting an FPGA

14. Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC

15. Chapter 12: Building a Complex Software with an Embedded Operating System Flow

16. Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs

17. Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs

18. Index

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19. Other Books You May Enjoy

Questions

Answer the following questions to test your knowledge of this chapter:

Is it possible to program the FPGA using the Vitis IDE? How would you do that?
If the MicroBlaze executable is hosted in the LMB BRAM, which utility is used to integrate it into the FPGA bitstream file?
Why do we need to initialize the LMB BRAM with the MicroBlaze executable prior to configuring the FPGA SoC?
Describe the steps used in the Vitis IDE to update the FPGA SoC bitstream using a new MicroBlaze executable ELF file.
What is QEMU?
What are the characteristics of the Xilinx QEMU? Which processors from Xilinx SoCs does it support?
Describe the steps to launch QEMU from the Vitis IDE.
How different is debugging the Cortex-A9 software using the Xilinx port of QEMU in comparison to using a real hardware board?
Describe the steps needed to debug the Cortex-A9 software on the QEMU emulator.
How can we profile the Cortex-A9 software?

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Table of Contents (20) Chapters

Questions

Authors (1)

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Table of Contents (20) Chapters

Questions

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