Project 13 – Handling the keyboard

We’ve looked at what the PS/2 protocol looks like. Let’s now put together a simple interface so that we can test our knowledge before we move on to our design integration. The first step is that we need to debounce our PS/2 signals. I’ve put together a debounce circuit and testbench so we can verify it. This cannot be built as is, but let’s look at it. Open up https://github.com/PacktPublishing/The-FPGA-Programming-Handbook-Second-Edition/blob/main/CH11/SystemVerilog/build/debounce.xpr. This version of the code will act as a reusable core. We want to make sure that we only change state after we’ve seen the CYCLES number of the same value. This will act as our debouncing circuit.

The interface is straightforward, as we can see in the following code:

SystemVerilog

module debounce
  #(parameter   CYCLES = 16)
  (input wire   clk,
   input wire   reset,
   input wire   sig_in,
   output logic sig_out...