You're reading from Architecting and Building High-Speed SoCs Design, develop, and debug complex FPGA based systems-on-chip

Product type Paperback

Published in Dec 2022

Publisher Packt

ISBN-13 9781801810999

Length 426 pages

Edition 1st Edition

Tools

FPGA

Concepts

Design

Author (1):

Mounir Maaref

View More author details

Table of Contents (20) Chapters

Preface

1. Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs

2. Chapter 1: Introducing FPGA Devices and SoCs FREE CHAPTER

3. Chapter 2: FPGA Devices and SoC Design Tools

4. Chapter 3: Basic and Advanced On-Chip Busses and Interconnects

5. Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects

6. Chapter 5: Basic and Advanced SoC Interfaces

7. Part 2: Implementing High-Speed SoC Designs in an FPGA

8. Chapter 6: What Goes Where in a High-Speed SoC Design

9. Chapter 7: FPGA SoC Hardware Design and Verification Flow

10. Chapter 8: FPGA SoC Software Design Flow

11. Chapter 9: SoC Design Hardware and Software Integration

12. Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs

13. Chapter 10: Building a Complex SoC Hardware Targeting an FPGA

14. Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC

15. Chapter 12: Building a Complex Software with an Embedded Operating System Flow

16. Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs

17. Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs

18. Index

Why subscribe?

19. Other Books You May Enjoy

Design capture of an FPGA SoC hardware subsystem

In this section, we start the building process of the ETS SoC hardware subsystem using the Xilinx Vivado tools. We will start by creating a Vivado project, adding the required subsystem IPs, configuring them, and connecting them to form the SoC using the IP Integrator utility of Vivado. But first, we will create a Vivado project that targets one of the Zynq-7000 SoC demo boards, if we have it at hand; we can then use it to verify the final functionality of the ETS SoC once we have built software for it. Also, any available demo board capable of hosting a Zynq-7000-based SoC design can be used as a target. These design capture steps were introduced in Chapter 2, FPGA Devices and SoC Design Tools, of this book, and we will build upon this information to achieve our current objective.