Make

The Make build system uses Makefiles. A Makefile is a text file with the name "Makefile" (exactly this and without any extension) in a source directory, and it contains build targets and commands that tell Make how to build the current code base.

Let's start with a simple multi-module C project and equip it with Make. The following shell box shows the files and directories found in the project. As you can see, it has one module named calc, and another module named exec is using it.

The output of the calc module would be a static object library, and the output of the exec module is an executable file:

$ tree ex23_1
ex23_1/
├── calc
│   ├── add.c
│   ├── calc.h
│   ├── multiply.c
│   └── subtract.c
└── exec
    └── main.c
2 directories, 5 files 
$

Shell Box 23-1: The...